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LF-Building-a-RISC-V-CPU-Core
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Made values hexadecimal in VIZ for full test program.

This commit is contained in:
Steve Hoover 2021-02-26 20:17:40 -05:00
parent 3de301a7ed
commit 4ed61feeeb
1 changed files with 2 additions and 0 deletions
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2
lib/risc-v_shell_lib.tlv
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@ -99,6 +99,8 @@ m4+definitions(['
m4_asm(ADDI, x30, x0, 1) m4_asm(ADDI, x30, x0, 1)
m4_asm(JAL, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0) m4_asm(JAL, x0, 0) // Done. Jump to itself (infinite loop). (Up to 20-bit signed immediate plus implicit 0 bit (unlike JALR) provides byte address; last immediate bit should also be 0)
m4_define(['M4_VIZ_BASE'], 16) // (Note that immediate values are shown in disassembled instructions in binary and signed decimal in decoder regardless of this setting.)
m4_define(['M4_MAX_CYC'], 70) m4_define(['M4_MAX_CYC'], 70)
'])m4_ifelse(['$1'], [''], ['m4_asm_end()'], ['m4_asm_end_tlv()'])']) '])m4_ifelse(['$1'], [''], ['m4_asm_end()'], ['m4_asm_end_tlv()'])'])