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Added banner, course link, and next steps links.

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Steve Hoover 2021-03-01 16:29:27 -05:00
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# Building a RISC-V CPU Core # Building a RISC-V CPU Core
Accompanying resources for the [Building a RISC-V CPU Core](https://courses.edx.org/TBD) [EdX](https://edx.org/) course by [Steve Hoover](https://www.linkedin.com/in/steve-hoover-a44b607/) of [Redwood EDA](https://redwoodeda.com), [Linux Foundation](https://www.linuxfoundation.org/), and [RISC-V International](https://riscv.org). Accompanying resources for the [Building a RISC-V CPU Core](https://www.edx.org/course/building-a-risc-v-cpu-core) [EdX](https://edx.org/) course by [Steve Hoover](https://www.linkedin.com/in/steve-hoover-a44b607/) of [Redwood EDA](https://redwoodeda.com), [Linux Foundation](https://www.linuxfoundation.org/), and [RISC-V International](https://riscv.org).
![VIZ](LF_VIZ.png)
## Welcome ## Welcome
@ -19,3 +21,17 @@ In case you get stuck, we've got your back! These <a href="https://makerchip.com
Here's a pre-built logic diagram of the final CPU. Ctrl-click here to [explore in its own tab](https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/riscv.svg). Here's a pre-built logic diagram of the final CPU. Ctrl-click here to [explore in its own tab](https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/riscv.svg).
![Final Core](lib/riscv.svg) ![Final Core](lib/riscv.svg)
## Finished!
Congratulations!!!
After completing this course, we hope you are inspired to continue your journey. These ideas might help:
- Try the tutorials in [Makerchip](https://makerchip.com).
- Learn more about [TL-Verilog](https://redwoodeda.com/tl-verilog).
- Explore the [RISC-V](https://riscv.org) ecosystem.
- Take [other courses](https://training.linuxfoundation.org/full-catalog/) from [Linux Foundation](https://www.linuxfoundation.org/)
- Discover [other training](https://www.redwoodeda.com/publications) from [Redwood EDA](https://redwoodeda.com)
- Get your core running on real hardware using FPGAs [in the cloud](https://github.com/stevehoover/1st-CLaaS) or [on your desktop](https://github.com/shivanishah269/risc-v-core/).
- Install [TL-Verilog tools](https://www.redwoodeda.com/products).
- Learn about the [WARP-V](https://github.com/stevehoover/warp-v) TL-Verilog CPU core generator.