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LF-Building-a-RISC-V-CPU-Core
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Removed bug workaround.

This commit is contained in:
Steve Hoover 2021-08-26 11:44:43 -04:00
parent 9dea12acf9
commit 0e71e94d9c
1 changed files with 0 additions and 3 deletions
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3
risc-v_solutions.tlv
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@ -18,7 +18,6 @@
// ---------------------------------- // ----------------------------------
// Include solutions. // Include solutions.
m4_define(['M4_FMT_NO_SOURCE'], 1)
m4_include_makerchip_hidden(['LF_workshop_solutions.private.tlv']) m4_include_makerchip_hidden(['LF_workshop_solutions.private.tlv'])
\SV \SV
@ -26,8 +25,6 @@
// stimulus support, and Verilator config. // stimulus support, and Verilator config.
m4_makerchip_module // (Expanded in Nav-TLV pane.) m4_makerchip_module // (Expanded in Nav-TLV pane.)
\TLV \TLV
\source ./LFworkshopsolutions.private.tlv 7
\end_source
//=================\ //=================\
// Choose Your Lab | // Choose Your Lab |