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LF-Building-a-RISC-V-CPU-Core/README.md

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Update README.md
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# Building a RISC-V CPU Core
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Accompanying resources for the [Building a RISC-V CPU Core](https://courses.edx.org/TBD) [EdX](https://edx.org/) course by [Steve Hoover](https://www.linkedin.com/in/steve-hoover-a44b607/) of [Redwood EDA](https://redwoodeda.com), [Linux Foundation](https://www.linuxfoundation.org/), and [RISC-V International](https://riscv.org).
Update README.md
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Resolving issue with m4_asm_end which must be used from both \TLV and \SV context. Use of new signal goTo* functions in VIZ. Readme updates.
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## Welcome
Congratulations for taking this step to expand your knowledge of computer hardware.
At this time, there are no course corrections or platform issues to report. Please do let us know within the EdX platform if anything gets in your way. There's a great deal of infrastructure to maintain for the course, and we aim to keep it all running smoothly. Now, back to EdX.
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## RISC-V Starting-Point Code
Resolving issue with m4_asm_end which must be used from both \TLV and \SV context. Use of new signal goTo* functions in VIZ. Readme updates.
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To begin the first RISC-V lab, when instructed to do so, Ctrl-click this link to <a href="https://makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FLF-Building-a-RISC-V-CPU-Core%2Fmaster%2Frisc-v_shell.tlv" target="_blank" atom_fix="_">open starting-point code in makerchip</a>.
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## RISC-V Reference Solution
Resolving issue with m4_asm_end which must be used from both \TLV and \SV context. Use of new signal goTo* functions in VIZ. Readme updates.
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In case you get stuck, we've got your back! These <a href="https://makerchip.com/sandbox?code_url=https:%2F%2Fraw.githubusercontent.com%2Fstevehoover%2FLF-Building-a-RISC-V-CPU-Core%2Fmain%2Frisc-v_solutions.tlv" target="_blank" atom_fix="_">reference solutions</a> (Ctrl-click) will help with syntax, etc. without handing you the answers.
Update README.md
2021-02-08 18:50:44 +00:00
Resolving issue with m4_asm_end which must be used from both \TLV and \SV context. Use of new signal goTo* functions in VIZ. Readme updates.
2021-02-26 22:43:18 +00:00
Here's a pre-built logic diagram of the final CPU. Ctrl-click here to [explore in its own tab](https://raw.githubusercontent.com/stevehoover/LF-Building-a-RISC-V-CPU-Core/main/lib/riscv.svg).
initial - riscv files
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![Final Core](lib/riscv.svg)